1. Field
The present embodiments discussed herein are directed to semiconductor devices. For example, the embodiment may be directed to a semiconductor device having a ferroelectric capacitor and fabrication process thereof.
2. Description of the Related Art
A ferroelectric memory is a non-volatile voltage-driven semiconductor memory device and is characterized by preferable feature of high operational speed, low electric power consumption and non-volatility of information in that the information held therein is retained even when the electric power is turned off. Ferroelectric memories are already used in IC cards and other portable electronic apparatuses.
FIG. 1 is a cross-sectional diagram showing the construction of a ferroelectric memory device 10 called stacked type device.
Referring to FIG. 1, the ferroelectric memory device 10 is a so-called 1T1C device and includes two memory cell transistors formed in a device region 11A defined on a silicon substrate 11 by a device isolation region 11I such that the two memory cell transistors share a bit line.
More specifically, there is formed an n-type well in the silicon substrate 11 as the device region 11A, wherein there are formed, on the device region 11A, a first MOS transistor having a polysilicon gate electrode 13A and a second MOS transistor having a polysilicon gate electrode 13B via respective gate insulation films 12A and 12B.
Further, LDD regions 11a and 11b of p−-type are formed in the silicon substrate 11 in correspondence to respective sidewalls of the gate electrode 13A. Similarly, LDD regions 11c and 11d of p−-type are formed in the silicon substrate 11 in correspondence to respective sidewalls of the gate electrode 13B. Thereby, the first and second MOS transistors are formed commonly in the device region 11A, and thus, the same p−type diffusion region is used as the LDD region 11b and the LDD region 11c. 
On the polysilicon gate electrode 13A, there is formed a silicide layer 14A, while on the polysilicon gate electrode 13B, there is formed a silicide layer 14B. Further, respective sidewall insulation films are formed on both sidewall surfaces of the polysilicon gate electrodes 13A and 13B.
Furthermore, diffusion regions 11e and 11f of p+-type are formed in the silicon substrate 11 at respective outer sides of the sidewall insulation films of the gate electrode 13A, and diffusion regions 11g and 11h of p+-type are formed in the silicon substrate 11 at respective outer sides of the sidewall insulation films of the gate electrode 13B. Thereby, the same p+-type diffusion region is used commonly for the diffusion regions 11f and 11g. 
Further, on the silicon substrate 11, there is formed an SiON film 15 so as to cover the gate electrode 13A including the silicide layer 14A and the sidewall insulation films of the gate electrode 13A and so as to cover the gate electrode 13B including the silicide layer 14B and the sidewall insulation films on the gate electrode 13B, and an interlayer insulation film 16 of SiO2 is formed on the SiON film 15. Further, contact holes 16A, 16B and 16C are formed in the interlayer insulation film 16 so as to expose the diffusion region 11e, the diffusion region 11f (the diffusion region 11g), and the diffusion region 11h, respectively, wherein via-plugs 17A, 17B and 17C of W (tungsten) are formed in the respective contact holes 16A, 16B and 16C via adhesive layers 17a, 17b and 17c, wherein each of the adhesive layers 17a, 17b and 17c is formed by lamination of a Ti film and a TiN film.
Further, on the interlayer insulation film 16, there is formed a first ferroelectric capacitor C1 in which a lower electrode 18A, a polycrystalline ferroelectric film 19A and an upper electrode 20A are stacked in contact with the tungsten plug 17A. Similarly, a second ferroelectric capacitor C2 is formed on the interlayer insulation film 16 by stacking of a lower electrode 18C, a polycrystalline ferroelectric film 19C and an upper electrode 20C in contact with the tungsten plug 17C.
Further, a hydrogen barrier film 21 of Al2O3 is formed on the interlayer insulation film 16 so as to cover the ferroelectric capacitors C1 and C2, and a next interlayer insulation film 22 is formed further on the hydrogen barrier film 21.
Further, in the interlayer insulation film 22, there are formed a contact hole 22A exposing the upper electrode 20A of the ferroelectric capacitor C1, a contact hole 22B exposing the via-plug 17B, and a contact hole 22C exposing the upper electrode 20C of the ferroelectric capacitor C2, wherein the contact holes 22A-22C are formed respectively with tungsten plugs 23A, 23B and 23C via respective adhesive layers 23a, 23b and 23c formed by lamination of a Ti film and a TiN film.
Further, Al interconnection patterns 24A, 24B and 24C are formed on the interlayer insulation film 22 respectively in correspondence to the tungsten plugs 23A, 23B and 23C with a barrier metal film of the Ti/TiN layered structure.
Patent Reference 1
Japanese Laid-Open Patent Application 2004-153031
Patent Reference 2
Japanese Laid-Open Patent Application 8-76352
Patent Reference 3
Japanese Laid-Open Patent Application 1-149423